Synopsys Customizes IP for Low-Voltage Chip Design

Synopsys has developed a customized memory compiler architecture for a new chip aimed at enhancing optical network infrastructure, particularly to support the demand for edge AI. This chip, designed to operate reliably at just 0.4 volts, faced significant hurdles due to the inherent challenges of stability and efficiency at such low voltages, which necessitated cooperation between Synopsys and their customer. This collaboration led to innovative adjustments in memory bit cell designs and the implementation of advanced low-leakage transistors to ensure reliability and performance. The achievement of this project demonstrates a shift in the market towards tailored IP solutions, crucial for meeting aggressive power-performance-area goals under stringent timelines. By adopting these innovative technologies, Synopsys is establishing a pathway toward greater domestic capabilities in AI hardware, reducing reliance on foreign technology. This project exemplifies the growing trend of localized solutions in the semiconductor space, enhancing national AI autonomy in critical infrastructure.