Broadcom Expands Vertical Compute with 3.5D Stacking Technology
Broadcom's 3.5D stacking could set a new standard by 2027, reshaping semiconductor design towards vertical efficiency.
What Changed
Broadcom has announced the development of its 3.5D Extreme Dimension System in Package (XDSiP) technology, which advances beyond the known 2.5D interconnect solutions. Historically, the shift from 2D to multidimensional stacking, like AMD’s pioneering 3D stacking techniques, has been gradual. Unlike existing approaches, Broadcom's 3.5D stacking involves not just stacking L3 cache as seen in AMD's Epyc CPUs but also aims to integrate multiple compute chiplets with HBM memory stacks.
Strategic Implications
This development shifts capabilities significantly by enabling reduced latency and power consumption in compute systems, crucial for high-performance computing and AI applications. Companies reliant on advanced node processes, such as AMD and Intel, will see direct benefits in efficiency. Broadcom is positioning itself as a key enabler of semiconductor innovation, which could tilt industry leverage towards companies mastering advanced packaging.
What Happens Next
Key stakeholders like chipset manufacturers are likely to adopt this technology to optimize their product offerings by 2027. This could trigger a response from competitors to upgrade their own stacking protocols. Policymakers might also take an interest in securing this tech under national innovation strategies to strengthen geopolitical tech autonomy.
Second-Order Effects
The introduction of 3.5D stacking may affect supply chains, particularly those dealing in traditional 2D and 2.5D components. As more manufacturers adopt this technology, there could be increased pressure on suppliers to innovate further in die-level interconnectivity and cooling solutions to address denser compute assemblages.
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