Hardware·Americas

Packetized Bus Innovation Transforms SoC Test Processes

Global AI Watch · Editorial Team··5 min read
Packetized Bus Innovation Transforms SoC Test Processes
Editorial Insight

This development shifts testing power to engineers, reducing foreign AI tool reliance and enhancing domestic capabilities.

Key Points

  • 1Third major SoC infrastructure advancement since 2025, increasing test efficiency by 40%.
  • 2Enhances engineers' capabilities, reduces dependency on manual calibration tools.
  • 3Strengthens domestic chip industry's control over testing processes, reducing foreign AI tool reliance.

What Changed

The introduction of the packetized bus for scan data delivery within Systems-on-Chip (SoC) marks a significant shift in semiconductor testing. Traditionally, core scan channel allocation methods constrained test processes to specific IO bandwidth limits. With the SSN bus, this flexibility in optimizing packet delivery for different core sizes or test conditions has now become possible. This advancement ranks alongside notable infrastructure changes in the silicon industry over the past year, providing a framework for enhanced data delivery methods well beyond standard applications.

Strategic Implications

The major beneficiaries of this development are semiconductor manufacturers, particularly those who adopt these systems early. By reducing reliance on traditional and often slower channel allocation methods, the SSN bus enhances diagnostic precision and efficiency. This shift empowers engineers with the ability to focus on optimizing their designs without being limited by hardware constraints, thereby leveraging AI more effectively. As engineers gain this heightened capability, the influence of AI as a standalone tool diminishes, positioning it as an augmentative resource rather than a replacement for human oversight.

What Happens Next

Expect the rollout of Agentic AI capabilities by the end of this year. These capabilities will further shorten the decision-making time for engineers in design-for-test (DFT) planning and debugging processes. Siemens EDA, with its established presence in the industry, is likely to play a pivotal role in driving these advancements forward. As these technologies become mainstream, standardized policy responses supporting innovation while safeguarding data security may emerge by mid-2027.

Second-Order Effects

Beyond immediate technical benefits, SSN's impact could extend to supply chain dynamics. By minimizing reliance on foreign-developed AI solutions for test processes, domestic industries can bolster their semiconductor sovereignty. This domestic capacity building might spark a wave of similar innovations across tech-centric nations, gradually reducing international dependencies.

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